Correlator System
Introduction
The digital backend is the section of the G.M.R.T. which deals with the digital conversion, manipulation and storage of the analog signals coming from the baseband system. The signal from the antenna after going through the baseband system is analog in form. This signal needs to be converted into digital form, so that it could easily be worked upon using digital signal processing. The signal after being converted into digital form is processed through FX Correlator to generate cross amplitude and phase information among the 30 antennas to synthesise the Stokes Parameters. The output of the correlator ( FFT subsystem ) is given in parallel to the Array Combiner for generating the Incoherent Array ( IA ) and Phased Array ( PA ) outputs for pulsar observations.
Features
NEW HARDWARE CORRELATOR :
* More processing bandwidth using the latest FPGA technology in collaboration with SKA South Africa.
* 32 Stations , dual pol. correlator using CASPER tools.
SOFTWARE CORRELATOR : GMRT SOFTWARE CORRELATOR BACKEND (GSB) :
* Better frequency resolution for full bandwidth case ie. longer FFT lengths.
* More Dynamic range ie. more bits per sample for better protection against radio frequency interference (RFI).
* Ability to filter out impulsive RFI and powerline RFI from raw data / visibility data.
* Ability to record raw data from each antenna and play back with different options.
* Ability to add new, sophisticated algorithms.
* Ability to form multiple beams within the primary beam (in phased array mode).
Technical Details
NEW HARDWARE CORRELATOR :
- iADC with max 1Gs/s capability, operating at 800MS/s ,atmel/E2V 84AD001BCT, analog input channels 2 , 1 clock and 1 sync inputs ,output LVDS through Z-DOK connector compatible to CASPER H/Ws iBOB & ROACH BOARDS.
- iBOB : VIRTEX 2 PRO FPGA.
- ROACH: VIRTEX 5 SX 95.
- Processing Bandwidth is 400MHz.
- FFT 1 Kpt real.
SOFTWARE CORRELATOR : GMRT SOFTWARE CORRELATOR BACKEND (GSB) :
Two Operating modes of S/W back-end : - Real-time data acquisition + writing to disks off-line read-back of recorded data and
- computation Real-time data acquisition + computation.
Basic Methodology : - Run synchronous sampling on all 8 ADC boards (32 antennas) – 16/32 MHz BW.
- Transfer data from ADC board to CPU unit (via the interrupt driven DMA)in large blocks (32 MB block size --> 8 MB per antenna).
- For recording mode, synchronous write to disk locally at each node.
- For correlations, distribute data from all antennas (using time division multiplexing) to all nodes -- each node handles 1/8 time slice from each block.
- Carry out FFT, fringe stop, MAC and other required operations at each node.
- Record integrated visibilities results to local disk on each node, or send them to collector nodes.
Required Specifications :
- Input data rate :32/64 Mega samples/sec per antenna --> 32 MB/sec (for 8-bit 16 MHz / 4-bit 32MHz).
- Computational Requirements : FFT ops per node ~ 4.3 GFLOPS , MAC ops per node ~ 8 GFLOPS.
- Networking requirement : 32 MB to be transferred to and from each node in ~ 251 msec --> ~ 230 MB/sec bi-directional data transfer speed for each node.
Node configuration : - Dual core, dual processor Intel Xeon CPUs
- 2 GB RAM, 1 TB SATA RAID storage
- Dual Gigabit Ethernet ports
- 8-bit, 4 Channel, 100 MSPS, PCI-X compliant ADC card
- Data transfer from ADC card to memory using DMA @ 145 MB/s
System Status
NEW HARDWARE CORRELATOR :
Status:
- 2 ANTENNA single board pocket correlator with delay & fstop correction completed & tested for shorter baselines.
- 8 ANTENNA dual pol. packetized corrletor with delay & fstop correction under test.
SOFTWARE CORRELATOR :
Status at the II phase :
- 32 channel system (32 ant, 1 pol, 16 MHz) : Running at 1.5 x real-time rate for 16 MHz BW data. Thoughts at that time .....
- Extension to 32 ant, 2 pols, 16 MHz (GSB-32.2.16) by adding 8 more nodes.
- Extension to 32 ant, 2 pols, 32 MHz (GSB-32.2.32) by attaching more Compute only nodes to the cluster.
- Add : 1. 8 more nodes similar to existing ones.
- 2. 16 nodes of ~ 2x compute capability of present nodes (e.g. Same motherboard with quad core dual processor CPUs, instead of the dual core dual processor CPUs).
Contact
Prof. Yashwant Gupta | ygupta@ncra.tifr.res.in |
Prof. Jayaram N. Chengalur | chengalu@ncra.tifr.res.in |
Dr. Sandeep K. Sirothia | sirothia@ncra.tifr.res.in |
Shri Jayanta Roy | jroy@ncra.tifr.res.in |
Shri Ajith Kumar B. | ajit@gmrt.ncra.tifr.res.in |
Shri Irappa M. Halagali | irappa@gmrt.ncra.tifr.res.in |
Shri G. J. Shelton | shelton@gmrt.ncra.tifr.res.in |
Shri Sandeep C. Chaudhari | scc@gmrt.ncra.tifr.res.in |
Ms. Mekhala V. Muley | mekhala@gmrt.ncra.tifr.res.in |
Shri Sanjay S. Kudale | ksanjay@gmrt.ncra.tifr.res.in |
Shri I. S. Bhonde | bkumar@gmrt.ncra.tifr.res.in |
Shri R. Balasubramaniam | rbalu@gmrt.ncra.tifr.res.in |
Shri S. Suresh Kumar | skumar@gmrt.ncra.tifr.res.in |
Shri B. Rajendran | raj@gmrt.ncra.tifr.res.in |
Shri C. P. Kanade | cpk@gmrt.ncra.tifr.res.in |
Shri M. Gopinathan | gopi@gmrt.ncra.tifr.res.in |
Peoples done invaluable contributions to the Digital backend in the past are;
Prof. C. R. Subramanya |
Shri Abhijit Dutta |
Shri Rakesh Malik |
Shri Vivek Tatke |
Ms. Alka Dikshit |
Shri Umesh Puranik |
Shri Izak S. |
Dr. Anish Roshi |
Shri sylvain Alliot |
Prof. A. Pramesh Rao |
Shri S. Ravi |
Shri Goutam Chattopadhyay |
Ms. Sulekha Deswandikar |
Shri Mahesh P. Burse |
Shri Kiran H. Dahimiwal |
Shri Ganesh S. Jangam |
Shri Ramchandra M. Dabade |
Shri T. L. Venkatasubramani |
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